Questions / Quant development, Concurrency & coordination
Different variables, same cache line
Two threads update independent counters that happen to occupy the same cache line. Correctness is synchronized, but performance degrades. What phenomenon should be investigated?
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Answer: C. False sharing of the counters' cache line.
- Cache coherence commonly tracks ownership at cache-line granularity. A write to either counter can invalidate the other core's copy of that line.
- Repeated transfers can slow independent updates. This fits false sharing rather than proving a correctness defect.
Interview shortcut. Independent hot writes on one cache line: false sharing.
Takeaway. Hardware sharing granularity can exceed the program's data-sharing granularity.
Why the other choices fail
- True sharing of one counter. The premise says the counters are independent. Contention can occur because hardware transfers their containing line, even without shared logical data.
- Lock convoying, since the counters may share a mutex. The counters are independent; no shared mutex is described.
- A data race caused solely by equal cache-line addresses. Sharing a line does not itself create a language-level race. The accesses are stated to be correctly synchronized.
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